Apparatus and method for argon plasma induced ultraviolet light curing step for increasing silicon-containing photoresist selectivity

ABSTRACT

Provided is a method and apparatus for increasing an etching selectivity of photoresist material. An exemplary method initiates with providing a substrate with a developed photoresist layer. The developed photoresist layer on the substrate includes polymer chains containing silicon. Next, the substrate and developed photoresist layer are exposed to an ultraviolet (UV) light, where the UV light emanates from a UV generating agent. A portion of the developed photoresist layer is then converted to a hardened layer where the hardened layer is created by cross-linking the polymer chains containing silicon and the cross-linking is activated by the UV light. Next an etch may be performed on the substrate using the hardened layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional to copending prior U.S. patentapplication Ser. No. 09/894,230, filed Jun. 27, 2001, and entitled“APPARATUS AND METHOD FOR ARGON PLASMA INDUCED ULTRAVIOLET LIGHT CURINGSTEP OR INCREASING SILICON-CONTAINING PHOTORESIST SELECTIVITY.” Thisapplication is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to lithography and more particularly toa method and apparatus for increasing the selectivity of asilicon-containing photoresist layer to improve profile control ofetched features without decreasing wafer throughput.

2. Description of the Related Art

The ability to work selectively on small well defined areas of asubstrate is paramount in the manufacture of semiconductor devices. Inthe continuing quest to achieve higher levels of performance and higherfunctional density of the semiconductor devices, the microelectronicsindustry is committed to applying new processes to further reduce theminimum feature sizes of the semiconductor devices.

As the feature sizes are reduced, the devices can become smaller orremain the same size but become more densely packed. As such, advancesin lithographic technologies used to pattern the semiconductor devicesmust keep pace with the progress to reduce feature sizes, in order toallow for smaller and more dense. For example, one of the main ways toreduce the device critical dimensions (CD) through lithographictechnologies has been to continually reduce the wavelength of theradiation used to expose the photoresist.

Sharp lithographic transmission becomes more of a challenge as wafersprogress to higher density chips with shrinking geometries. Furthermore,as metallization transitions to dual damascene processes, lithographytechniques to pattern holes or trenches in the dielectric become morecritical. In particular, the photoresists employed in the lithographictechniques must provide for proper selectivity so that downstreametching processes yield sharp profiles. Moreover, as device featuresprogressively become smaller, the aspect ratios for those same featuresbecome greater, thereby making it more difficult to accurately performetching operations.

Photoresists are typically polymeric materials consisting ofmulti-component formulations. Additionally, a photoresist may be appliedas a single layer or as multiple layers where one of the layers containssilicon. Multi-layered photoresists tend to offer superior formation ofa pattern, therefore, the multi-layered photoresists are desirable assemiconductor devices become smaller. However, resist compositionscontaining silicon, either in the main resist polymer or bypost-exposure surface treatment (e.g., silylation), have either failedto deliver adequate improvement in etch resistance or have had poorprocessing performance due to the unacceptable selectivity past thesilicon containing layer.

As a result, there is a need to solve the problems of the prior art toimprove the selectivity past the developed photoresist layer containingsilicon, without simultaneously decreasing wafer throughput, so thatduring etching there is improved ability to distinguish between siliconcontaining photoresists and non silicon containing photoresists or thedielectric.

SUMMARY OF THE INVENTION

Broadly speaking, the present invention fills these needs by providing aphotoresist layer that has been hardened to increase the selectivity ofthe hardened photoresist layer relative to an underlying photoresist orunderlying dielectric. In addition, the hardening process may take placein an etch chamber so that the fabrication, e.g., etching steps, may becombined with treating processes to improve wafer throughput. It shouldbe appreciated that the present invention can be implemented in numerousways, including as an apparatus, a system, a device, or a method.Several inventive embodiments of the present invention are describedbelow.

In one embodiment, an apparatus for exposing a photoresist-developedsubstrate is provided. In this embodiment, a chamber is included wherethe chamber has at least one gas inlet adapted to introduce a gas intothe chamber. Also included is a support within the chamber. A substrateon the support where the substrate has at least one developedphotoresist layer is included. The substrate is exposed to anultraviolet (UV) light within the chamber where the UV light isgenerated from a UV generating agent The exposure of the developedphotoresist to the UV light causes at least a portion of the developedphotoresist layer to transform to a hardened layer.

In another embodiment of the invention an apparatus for curing aphotoresist is provided. In this embodiment, a chamber having at leastone gas inlet adapted for introducing an ultraviolet (UV) generatingagent into the chamber and a support within the chamber are included. Asubstrate, on the support, where the substrate has a first photoresistlayer and a second photoresist layer is included, where the firstphotoresist layer is disposed over the second photoresist layer. Thefirst photoresist layer includes silicon containing polymer chains. Thesilicon containing polymer chains are cross-linked upon exposure to UVlight to form a hardened layer at a top region of the first photoresistlayer, where the UV light is generated by the UV generating agent.

In yet another embodiment of the invention, a method for increasing aselectivity of a photoresist is provided. The method initiates withproviding a substrate with a developed photoresist layer, the developedphotoresist layer including polymer chains containing silicon. Next, thesubstrate is exposed to an ultraviolet (UV) light, where the UV lightemanates from a UV generating agent. Finally, a portion of the developedphotoresist layer is converted to a hardened layer where the hardenedlayer is created by cross-linking the polymer chains containing silicon,where the cross-linking is activated by UV light.

In still another embodiment of the invention, a method for curing aphotoresist is provided. The method initiates with providing a substratewith a first photoresist layer and a second photoresist layer. The firstphotoresist layer is developed and disposed over the second photoresistlayer and the first photoresist layer is formulated to include polymerchains containing silicon. Next, the first photoresist layer is exposedto ultraviolet (UV) light where the UV light emanates from a UVgenerating agent. The method terminates after converting a portion ofthe first photoresist layer to a hardened layer where the hardened layeris configured to increase an etching selectivity ratio.

In still yet another embodiment, a method for curing a photoresistdisposed on a wafer in an etch chamber is provided. The method initiateswith introducing an ultraviolet (UV) generating agent into an etchchamber through a process gas inlet of the etch chamber. The UVgenerating agent is induced to emit UV light. Next, the wafer is exposedto the UV light where the wafer has a developed photoresist layerformulated to include polymer chains containing silicon. Then, a portionof the developed photoresist layer is converted to a hardened layer uponexposure to the UV light.

The advantages of the present invention are numerous. Most notably, theformation of the hardened layer increases the selectivity ratio of theunderlying photoresist layer or interlayer dielectric relative to thehardened layer of the top photoresist layer. Accordingly, any etchprocesses performed on the substrate with the hardened layer will etchthrough the underlying photoresist layer or interlayer dielectric at anincreased rate relative to the etch rate of the hardened layer.Furthermore, the etch profile control will be improved as a result ofthe increased selectivity, thereby allowing for pinpoint accuracy assemiconductor feature size continues to shrink. Additionally, an etchchamber may be utilized for curing the hardened layer. As a result,after the curing process, the substrate may be etched in the samechamber. Hence, throughput is increased and handling of the substrate isminimized.

Other aspects and advantages of the invention will become apparent fromthe following detailed description, taken in conjunction with theaccompanying drawings, illustrating by way of example the principles ofthe invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be readily understood by the followingdetailed description in conjunction with the accompanying drawings, andlike reference numerals designate like structural elements.

FIG. 1 illustrates a block diagram displaying a substrate in which thetop photoresist layer is being exposed prior to development inaccordance with one embodiment of the invention.

FIG. 2 illustrates block diagram depicting a developed substrate.

FIG. 3 illustrates block diagram depicting a developed photoresist beingexposed to an ultraviolet (UV) light in accordance with one embodimentof the invention.

FIG. 4 illustrates block diagram depicting an etched substrate having apost-etched hardened top layer of a silicon-containing photoresist.

FIG. 5 illustrates flowchart depicting a method for increasing asilicon-containing photoresist selectivity in accordance with oneembodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An invention is described for an apparatus and a method for enhancingthe selectivity of a silicon containing photoresist thereby improvingetch profile control. It will be obvious, however, to one skilled in theart, that the present invention may be practiced without some or all ofthese specific details. In other instances, well known processoperations have not been described in detail in order not tounnecessarily obscure the present invention.

The embodiments of the present invention provide an apparatus and methodfor an improved selectivity of a silicon-containing photoresist which inturn, allows for amelioration of a subsequent etch profile. In oneembodiment, a hardened layer is formed in a silicon-containingphotoresist by exposing the developed silicon-containing photoresist toultraviolet (UV) light. In accordance with one embodiment of theinvention, the UV light is generated by striking a plasma containing aninert gas such as neon, as will be described below in more detail. Theexposure to the UV light causes the polymer chains of the siliconcontaining photoresist to cross link, thereby creating a hardened layer.

The hardened layer of the silicon-containing photoresist has anincreased selectivity relative to an underlying photoresist layer or anunderlying interlayer dielectric (ILD). Accordingly, the increasedselectivity allows for tighter control of future etching processes,particularly with respect to dual damascene processing. Just assignificant, the formation of the hardened layer can take place in anetch chamber. Correspondingly, the etch chamber is configured to controlvarious process parameters as discussed below. In addition, once thesilicon-containing photoresist has been hardened, downstream etchingprocesses may occur in the etch chamber without the need to remove thewafer. Consequently, wafer throughput is increased by combiningfabrication steps into a single system.

FIG. 1 illustrates a block diagram 100, displaying a substrate in whichthe top photoresist layer is being exposed to develop thesilicon-containing photoresist in accordance with one embodiment of theinvention. In FIG. 1, light 102 from a light source (not shown) passesthrough a glass reticle 104. The light 102 will not pass through thereticle in the opaque areas 106. In accordance with one embodiment ofthe invention, the light 102 is ultraviolet (UV) light. It should beappreciated that the source of the UV light here is a mercury arc lampor excimer laser and is applied as part of the development process.Typically, for a positive resist, the UV light causes a photoacidgenerator to generate an acid in the exposed regions. Thereafter, duringpost-exposure bake of the development process the resist is heatedcausing an acid-catalyzed deprotection reaction. The elevatedtemperature during post-exposure bake is required for the exposed resistto become soluble in the developer solution. The exposure to UV lightprior to development of the photoresist is distinct from the embodimentsof the present invention which occur post-exposure.

Continuing with FIG. 1, the light 102 passes through the unblocked areas124 of the reticle 104 to the substrate 122. The substrate 122 containsa top layer 110 of silicon-containing photoresist over a second layer116 of a non silicon-containing photoresist. An example of thesilicon-containing photoresist is Fuji film TIS-200-IL-7 and an exampleof the non silicon-photoresist is Fuji film TIS-200-IL-5, both of whichmay be purchased from Arch Chemicals, Inc. of Norwalk CT. As depicted inFIG. 1, the second layer of non silicon-containing oxide resides over aninterlayer dielectric (ILD) 118. In accordance with one embodiment ofthe invention the ILD 118 is silicon dioxide. In a dual-damascenestructure, metal lines 120 are formed in another ILD 118′. The metallines 120 are copper in accordance with one embodiment of the invention.Although, the underlying features can be any features, so long as accessis made to them by etching. The etching performance, however, issignificantly improved due to the robust selectivity provided by thepost developed UV exposure, which is disclosed below.

FIG. 2 illustrates block diagram 128 depicting a developed substrate122. The top layer 110 of silicon-containing photoresist has beendeveloped to remove the silicon-containing photoresist from regions 130,which were exposed to light 102 of FIG. 1. Regions 112 of thesilicon-containing photoresist remain on the top layer of substrate 122.The bottom layer 116 of non silicon-containing photoresist remainsintact. As can be seen in FIG. 2, the development process removed thesilicon-containing photoresist to the border 132 between the top layer110 of photoresist and the bottom layer 116 of photoresist. Inaccordance with one embodiment of the invention, the development methodmay be continuous spray development, puddle development, etc. It shouldbe appreciated that the photoresist 114 exposed to UV light in FIG. 1,becomes more soluble as mentioned above, so that during development theexposed photoresist 114 is removed, as depicted in FIG. 2.

While the above exposure and development of the photoresist has beendescribed for a positive resist, it is understood that the apparatus andmethod is equally applicable for a negative resist. For example, with anegative resist, the reticle or mask 104 would be modified so as toexpose regions 112 and not expose regions 114 of the silicon-containingphotoresist layer 110. For this embodiment, the exposed regions 112become less soluble than unexposed region 114. The negative resist isthen developed by a solvent wash of the photoresist layer 110 to removeregions 114 in accordance with one embodiment of the invention.

FIG. 3 illustrates block diagram 134 depicting a developed photoresistbeing subjected to UV light in accordance with one embodiment of theinvention. Substrate 122 of diagram 134 contains a top layer 110 ofdeveloped silicon-containing photoresist. The substrate 122 and the topphotoresist layer is exposed to UV light 136. In one embodiment, the UVlight 136 is generated by striking a plasma. In a preferred embodiment,the plasma is a mixture of argon gas and neon gas, where the neon gas isthe UV generating agent. It should be appreciated that the argon-neonplasma emits UV light 136 which in turn causes the polymer chains of thesilicon-containing photoresist to cross link. In accordance with oneembodiment of the invention, the substrate layer 110 ofsilicon-containing photoresist is exposed to the UV light 136 emitted bythe plasma. For illustration purposes, the UV light 136 emitted by theplasma is depicted by arrows 136. The flow rate of the argon and neongases are controlled through the etch chamber controls, as will bedescribed in reference to FIG. 5. In still another embodiment of theinvention, the helium gas replaces neon gas as the UV generating agent.

Continuing with FIG. 3, the UV light interacts with the top layer 110 ofthe silicon-containing photoresist to form a hardened layer 138. Itshould be appreciated that the exposure to UV light causes the polymerchains of the silicon-containing photoresist to cross-link. Inaccordance with one embodiment of the invention, silicon-hydrogen (Si—H)and/or silicon-acetyl (Si—CH₃) bonds are formed to cross link thepolymer chains of the silicon-containing photoresist The cross linkedpolymer chains form a hardened layer 138. The etch selectivity of thehardened layer 138, relative to the bottom photoresist layer 116 or theILD 118, is greater due to the cross-linking of the polymer chains,which in turn creates a more impenetrable barrier for future etchprocesses. Accordingly, the etch process will yield sharper profiles aswell as accommodate high aspect ratio features that coincide withsmaller semiconductor devices.

In a preferred embodiment of the invention as illustrated in FIG. 5, thetop layer 110 of silicon-containing photoresist has a thickness of about2000 Å while the bottom layer 116 of non silicon-containing photoresisthas a thickness of about 6000 Å. In a general embodiment, thesilicon-containing photoresist has a thickness that ranges between 1000Å and about 3000 Å, while the bottom layer 116 of non silicon-containingphotoresist has a thickness that ranges between about 3000 A and about8000 Å. In another embodiment of the invention, the cross-linked layer138 has a thickness between about 5% to about 75% of the thickness ofthe original layer 110.

As can be seen in diagram 134 the remainder of the top layer of thesilicon-containing photoresist is unchanged as depicted by unconvertedregions 140. In addition, regions 142 of the lower photoresist layer 116of non silicon-containing photoresist are exposed to the UV light butare not cross-linked because of the lack of silicon in the lowerphotoresist layer 116. It should be appreciated that the conversionprocess may take place inside a chamber, such as an etch chamber whichhas a plurality of gas inlets. In such an embodiment the chamber isconfigured to control parameters, such as a flow rate of the argon andneon gases, a pressure inside the chamber, a temperature inside thechamber and the power of a top and bottom electrode. The preferredranges for these parameters are discussed in reference to FIG. 5. Justas significant, the use of an etch chamber allows for combining thedifferent fabrication steps i.e., hardening the photoresist layer 110and downstream etching, in a single system, thereby increasing waferthroughput.

FIG. 4 illustrates block diagram 146 depicting an etched substratehaving a post-etched hardened top layer 138 of a silicon-containingphotoresist. Block diagram 146 displays etch profiles 150 which havebeen etched into substrate 122. It should be appreciated that either dryetch or wet etch processes can be used to create etch profile for via150. As depicted by FIG. 4, the hardened layer 138 of the top layer 110of silicon-containing photoresist shows the effects of the etchingprocess, where the thickness of the hardened layer 138 has beendecreased through the etching process. In accordance with one embodimentof the invention, the etching process is part of a dual damasceneprocess where the interlayer dielectric 118 is etched down to coppermetallization line 120. It should be appreciated that for a dualdamascene process the etch may proceed through multiple dielectrics sothat copper interconnect wiring may be formed.

FIG. 4 displays a via 150 etched through the dielectric to the coppermetallization line 120. It can be appreciated that as devices furtherdecrease in size, the aspect ratio of the vias, i.e., the ratio of thevia depth to its width, increases. The higher aspect ratios requirehighly accurate etching to ensure device performance. As the aspectratio increases the etching selectivity of the photoresists needs toincrease so as to adequately protect the underlying dielectric. WhileFIG. 4 demonstrates a portion of the hardened layer 138 remaining on thesubstrate 122, if the selectivity of the hardened layer 138 was notincreased through the invention described herein, then the etchingprocess may etch through photoresist layers 110 and 116 into thedielectric 118. Accordingly, the further miniaturization of devicefeatures will continue to increase aspect ratios of the same features.As such, increasing the etching selectivity, as described herein, willensure underlying layers are adequately protected during the etchingprocess. While FIG. 4 depicts an etch of a via to the copperinterconnects, it should be understood that hardened photoresist layer138 is applicable for any type of dual damascene process including viafirst, trench first and self aligned processes

Still referring to FIG. 4, in accordance with one embodiment of theinvention, the etch rate of the hardened layer 138 of the top layer 110of the silicon-containing photoresist relative to the etch rate of thenon silicon-containing photoresist layer 116 decreases. Likewise, theetch rate of the hardened layer 138 relative to the etch rate of the ILD118 decreases. Accordingly, the selectivity ratio (S_(r)), defined bythe etch rate of the film undergoing the etch (E_(f)) divided by theetch rate of the photoresist (E_(r)), increases. The higher selectivitytranslates to the etching occurring on the desired layers, i.e., thematerial under the hardened layer 138 is shielded during etching as theetch rate of the hardened layer is smaller than the etch rate of the nonsilicon-containing photoresist 116 or the ILD 118. In accordance withone embodiment of the invention, the selectivity ratio (S_(r)) of asilicon cross-linked hardened layer 138 and the non silicon-containingphotoresist 116 is between about 8 and about 15. As further illustratedin FIG. 4, the hardened layer 138 effectively shields the layers belowit. It should be appreciated that in this embodiment, even if thehardened layer is etched away completely during the etching process, thenon silicon-containing layer is still available to shield theappropriate areas of the substrate from the etching process.

FIG. 5 illustrates flowchart 154 depicting a method for increasing asilicon-containing photoresist selectivity in accordance with oneembodiment of the invention. Flowchart 154 initializes with operation156 where a substrate with a developed photoresist is provided. Here,the substrate may include one or more photoresists with the topphotoresist being developed as discussed in reference to FIG. 1. Inaccordance with one embodiment of the invention, the developedphotoresist is a silicon-containing photoresist.

Flowchart 154 then proceeds to operation 158 where the top photoresistlayer is exposed to UV light generated by a UV light generating agent.Here, the exposure may be inside an etch chamber. Accordingly, thesubstrate will rest on a support within the chamber such as a chuck. Inaccordance with one embodiment of the invention, the UV light generatingagent is a neon-containing plasma. For example, a neon gas is introducedinto the etch chamber through process gas inlets, thereby creating thecuring environment to harden a silicon-containing photoresist when theplasma is struck. In a preferred embodiment, neon gas is provided to theetch chamber with an inert gas such as argon. Other UV generating agentsthat may be used include helium, hydrogen, krypton and xenon. It shouldbe further appreciated that the creation of the hardening layer may beinitiated by striking a plasma within the etch chamber and controllingcertain parameters inside the etch chamber as discussed below.

As is well known in the art, etch chambers are capable of controllingvarious parameters. In accordance with one embodiment of the invention,the flow rate of the process gases, the pressure and temperature withinthe chamber, and the power to the top and bottom electrodes arecontrolled within the ranges that follow. It should be appreciated thatthe following ranges are provided for illustration purposes only. Theflow rate of an inert gas for a carrier gas, such as argon, is betweenabout 1000 standard cubic centimeters per minute (sccm) to about 3000sccm with a preferred flow rate of about 2000 sccm. The flow rate forthe UV generating agent, such as neon, is between about 0.2% and about0.8% of the flow rate of the carrier gas such as argon with a preferredflow rate of about 0.4% of the carrier gas flow rate. The pressurewithin the chamber is controlled between about 1 Torr and about 5 Torrwith a preferred pressure of about 3 Torr. The temperature within thechamber is controlled between about −30° Celsius (C) and about 70° C.with a preferred temperature of about 0° C. The power to the topelectrode is between about 100 watts (W) and about 1500 W with apreferred power of about 600 W. The power to the bottom electrode isbetween about 0 W to about 1000 W with a preferred power of about 0 W.It should be appreciated that the above ranges may vary in differentetch chambers.

Returning back to FIG. 5, following operation 158 the method advances tooperation 160, where a portion of the first photoresist layer istransformed to a hardened layer. As mentioned previously, the UV lightinduces the hardening agent of the top photoresist layer to formcross-linked polymer chains with Si—H bonds and Si—CH₃ bonds. It shouldbe appreciated that the exposing the silicon-containing photoresist tothe UV light induces the polymers of the photoresist to form across-linked network of polymers from the previously singleuncross-linked polymer chains of the photoresist. In one embodiment ofthe invention the polymers are cross-linked through Si—H bonds andSi—CH₃ bonds. Finally the method terminates with operation 162, where anetch is performed using the hardened layer. Here, a via may be etched asshown in FIG. 4. Alternatively, a trench may be etched and siliconcontaining photoresist applied and hardened, as described above, todefine a region for etching a via.

As described above in reference to FIG. 3, the hardened layer 138 has athickness of about 50% of the original thickness of thesilicon-containing photoresist layer. It should be appreciated that thehardened layer 138 of the substrate will improve the selectivity forfuture etching of the substrate 122. In other words, the selectivity ofthe hardened layer relative to the bottom photoresist layer 116 and theILD 118 is increased, thereby ensuring optimal critical dimension andprofile control. In a preferred embodiment of the invention, theselectivity ratio between the hardened layer and the nonsilicon-containing photoresist or the ILD is between about 8 to about15.

It should be appreciated that the above described invention may beemployed with a single silicon-containing photoresist layer is usedwithout an underlying photoresist layer being applied to the substrate.Also, as mentioned above the invention may be utilized as part of a dualdamascene process or traditional metallization processes where aluminumalloy forms the metal lines.

Although the foregoing invention has been described in some detail forpurposes of clarity of understanding, it will be apparent that certainchanges and modifications may be practiced within the scope of theappended claims. Accordingly, the present embodiments are to beconsidered as illustrative and not restrictive, and the invention is notto be limited to the details given herein, but may be modified withinthe scope and equivalents of the appended claims.

1. An apparatus for exposing a photoresist-developed substrate,comprising: a chamber, the chamber having at least one gas inlet, thegas inlet being adapted to introduce a gas into the chamber; a supportwithin the chamber; and a substrate on the support, the substrate havingat least one developed photoresist layer, the substrate being exposed toultraviolet (UV) light within the chamber, the UV light being generatedfrom a UV generating agent, the exposure of the developed photoresist ofthe substrate causing at least a portion of the developed photoresistlayer to transform to a hardened layer.
 2. The apparatus as recited inclaim 1, wherein the developed photoresist layer is a silicon containingphotoresist.
 3. The apparatus as recited in claim 1, wherein the UVgenerating agent is neon.
 4. The apparatus as recited in claim 1,wherein the chamber is an etch chamber.
 5. The apparatus as recited inclaim 1, wherein the hardened layer has a thickness of between about 5%to about 75% of the thickness of the developed photoresist layer.
 6. Theapparatus as recited in claim 2, wherein the hardened layer includescross-linked polymer chains.
 7. The apparatus as recited in claim 1,wherein a temperature inside the chamber is between about −30 C. andabout 70 C.
 8. The apparatus as recited in claim 1, wherein argon gas issupplied to the chamber at a flow rate between about 1000 sccm and about3000 sccm.
 9. The apparatus as recited in claim 8, wherein neon gas issupplied to the chamber at a flow rate between about 0.2% and about 0.8%of the argon gas flow rate.
 10. An apparatus for curing a photoresist ona substrate, comprising: a chamber, the chamber having at least one gasinlet, the gas inlet being adapted to introduce an ultraviolet (UV)generating agent into the chamber; a support within the chamber; and asubstrate on the support, the substrate having a first photoresist layerand a second photoresist layer, the first photoresist layer beingdisposed over the second photoresist layer, the first photoresist layercomprising silicon containing polymer chains, the silicon containingpolymer chains cross-linking upon exposure to a UV light to form ahardened layer at a top region of the first photoresist layer, the UVlight being generated by the UV generating agent.
 11. The apparatus asrecited in claim 10, wherein the UV generating agent is neon.
 12. Theapparatus as recited in claim 10, wherein the support is a chuck. 13.The apparatus as recited in claim 10, wherein a thickness of the secondphotoresist layer is about 6000 521 .
 14. The apparatus as recited inclaim 10, wherein an etch selectivity ratio of the first photoresistlayer and the second photoresist layer is between about 8 and about 15.15. The apparatus as recited in claim 10, wherein the polymer chains arecross-linked by one of silicon-hydrogen bonds and silicon-acetyl bonds.16. A method for curing photoresist, comprising: providing a substratewith a first photoresist layer and a second photoresist layer, the firstphotoresist being developed and disposed over the second photoresistlayer, the first photoresist layer being formulated to include polymerchains containing silicon; exposing the first photoresist layer to anultraviolet (UV) light, the UV light emanating from a UV generatingagent; and converting a portion of the first photoresist layer to ahardened layer, the hardened layer being formed to increase an etchingselectivity ratio.
 17. The method for curing a photoresist as recited inclaim 16, wherein the UV generating agent is neon.
 18. The method forcuring a photoresist as recited in claim 16, wherein exposing the firstphotoresist layer to a UV light further includes, striking a plasmacontaining the UV generating agent to induce the generation of UV light.19. The method for curing a photoresist as recited in claim 16, whereinthe polymer chains are cross-linked through one of silicon-hydrogenbonds and silicon-acetyl bonds.
 20. The method for curing a photoresistas recited in claim 16, wherein the curing occurs within an etchchamber.
 21. In an etch chamber having a top and a bottom electrode,process gas inlets, and a chuck for holding a wafer, the wafer includinga dielectric layer to be etched, a method for curing a photoresistdisposed on the wafer, comprising: introducing an ultraviolet (UV)generating agent into an etch chamber through a process gas inlet, theUV generating agent being induced to emit UV light; exposing the waferto the UV light, the wafer having a developed photoresist layer, thedeveloped photoresist layer being formulated so as to include polymerchains containing silicon; and converting a portion of the developedphotoresist layer to a hardened layer upon exposure to the UV light. 22.The method for curing a photoresist as recited in claim 21, wherein theUV generating agent is neon.
 23. The method for curing a photoresist asrecited in claim 21, wherein converting a portion of the developedphotoresist further includes, cross-linking the polymer chains of thedeveloped photoresist.
 24. The method for curing a photoresist asrecited in claim 21, further comprising: controlling the gas flow rate,a temperature of the etch chamber, a pressure of the etch chamber, and apower supply to the top and the bottom electrode.
 25. The method forcuring a photoresist as recited in claim 21, wherein the portion of thephotoresist layer converted to a hardened layer is between about 5% andabout 75% of the photoresist layer.
 26. The method for curing aphotoresist as recited in claim 24, wherein the power to the topelectrode is maintained at between about 100 watts and 1500 watts. 27.The method for curing a photoresist as recited in claim 24, wherein thepower to the bottom electrode is maintained at between about 0 watts and1000 watts.